A current common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is an on-board or embedded array of memory storage elements. These elements may be provided as dynamic random access memory (DRAM) cells and alternatively as static random access memory cells (SRAM) cells. DRAM and SRAM memories are describes as “volatile” memory cells, in that if the power to the integrated circuit device is removed, the stored data will be lost. DRAM cells may be provided in very dense arrays, since a DRAM cell requires only a single access transistor and a storage capacitor, however DRAM circuits have relatively slow access time for reads and writes, and require somewhat complicated control circuitry, and each DRAM cell stores data as charge on a leaky capacitor, so that the DRAM array must be refreshed periodically to maintain state. This requires either that a processor periodically stop other operations and perform the refresh cycles, or that a dedicated memory controller (more often used in recently produced devices) perform the refresh cycles.
In contrast, SRAM memory arrays provide storage without the need for refresh cycles. SRAM arrays require more silicon area, since each bit cell is a latch typically formed of six transistors (6T) or more; however, the SRAM cells will retain data so long as an adequate supply voltage is present. Further advantages are that access times are very fast compared to DRAM cells, making SRAM cells particularly attractive as scratchpad or working data storage, such as cache memory for processors. Recent system on a chip (SOC) designs often incorporate one, two or more “cores”. These cores are predesigned popular processors such as DSPs, ARMs, RISC or microprocessors, often arranged with a level one (L1) cache memory of SRAM cells laid out near or adjacent to the processor to make very fast processor operations possible. In many devices a dual-core approach is used; for example, a radio transceiver core may be provided with a microprocessor core. Several SRAM arrays may be used in such integrated circuits.
Increasingly, integrated circuits are used to implement functions in battery operated devices. For example, SOCs may be used to provide all or most of the circuitry needed to implement the main functions of a cellphone, laptop computer, netbook computer, audio or video player, camcorder or camera, smartphone or PDA. In these devices, customer defined logic or licensed processor core designs may be integrated with other predefined or macro cells such as microprocessors, digital signal processors, cores such as ARM, RISC or similar core functions, cell phone modules, and the like.
In an SRAM bit cell, data is stored on two storage nodes which are inversely related. A pair of CMOS inverters, formed of four MOS transistors, is arranged as a latch cell, each storage node being formed of the gate terminals of two MOS transistors and receiving the output of an inverter formed of two MOS transistors in complementary MOS (CMOS) technology.
FIG. 1 depicts a typical single port SRAM bit cell 10 in a six transistor (6T) arrangement. In FIG. 1, a pair of MOS pass gates PG1 and PG2 couple a pair of data lines referred to as “bit lines” BL and BLB to inversely related storage nodes SN1 and SN2, respectively. The pass gate transistors PG1 and PG2 are typically formed of NMOS transistors as is known in the art. A positive supply voltage Vdd, which may be from 0.6 Volts to 3.0 or more volts, depending on the technology node, is shown. Pull up transistors PU1 and PU2 are formed of PMOS transistors and couple the positive supply to one or the other storage nodes, depending on the state of the SRAM cell 10. A second supply voltage Vss, usually placed at ground, is shown.
Two pull down transistors PD1 and PD2, which are also usually NMOS transistors, couple this negative or ground voltage Vss to one or the other storage nodes labeled SN1 and SN2, depending on the state of the bit cell. The 6T SRAM bit cell is a latch that will retain its data state indefinitely so long as the supplied power is sufficient to operate the circuit correctly. Two CMOS inverters formed of PU1, PD1 and PU2, PD2 are “cross coupled” and they operate to reinforce the stored charge on the storage nodes SN1 and SN2 continuously. The two storage nodes are inverted one from the other, as shown in the figure. When SN1 is a logical “1”, usually a high voltage, SN2 is at the same time a logical “0”, usually a low voltage, and vice versa.
When the single port SRAM bit cell 10 is written to, complementary write data signals are placed on the bit line pair BL and BLB. A positive control signal on a wordline WL is coupled to the gate of both pass gates PG1 and PG2. The transistors PU1, PD1 and PU2, PD2 are sized such that the data on the bit lines may overwrite the stored data and thus write, or program, the SRAM bit cell 10.
When the SRAM bit cell 10 is read from, a positive voltage is placed on the word line WL, and the pass gates PG1 and PG2 allow the bit lines BL and BLB to be coupled to, and receive the data from, the storage nodes SN1 and SN2. Unlike a dynamic memory cell, the SRAM bit cell does not lose its stored state during a read if the power supply Vdd is maintained at a sufficiently high level, so no “write back” operation is required after a cell read.
The bit lines BL and BLB form a complementary pair of data lines. As is known to those skilled in the art, these paired data lines may be coupled to a differential sense amplifier (not shown); the differential voltage can be sensed and amplified, as is known in the art. This amplified sensed output signal may then be output as data to other logic circuitry in the device.
FIG. 2 depicts another form of a conventional SRAM bit cell 12 that uses 8 transistors (8T) and has an additional functionality in the form of a read port 14. Thus this configuration may be referred to as a dual port or two port (2P) 8T SRAM bit cell. In FIG. 2, the 6T cell 10 such as is shown in FIG. 1 is used. SRAM bit cell 12 additionally has a read port 14 of two NMOS transistors, read port pull down transistor RPD and read port pass gate transistor RPG. A read word line (RWL) is provided that is dedicated to “reads” only. The previous word line WL in FIG. 1 now becomes a write only word line WWL in the 8T cell 12 of FIG. 2. Thus the 2P bit cell has a write port and a separate read port. Advantages of a separate read port are that the possibility of “read disturbs” is reduced, because the data stored in the bit cell is not affected by the read operations; instead, the read pull down transistor RPD is either on or off, based on the storage node SN2 voltage that is coupled to the gate terminal of the transistor RPD. Because an NMOS transistor has gain, the stored data signal at SN2 is amplified by the gain of transistor RPD; and when the read word line RWL has a positive voltage placed on it, read pass gate transistor RPG turns on and couples the read bit line RBL to the read pull down transistor RPD, and the read port therefore outputs a corresponding data bit on the read bit line RBL.
In many applications, SRAM arrays of many bit cells are used that store data or programs for retrieval and use later. The SRAM cells may experience many more read operations than write operations in the same time period. Thus, it is very advantageous to have the read operations isolated from the bit cell by the read port circuit 14. This is true even though the 8T cell uses slightly more layout area in silicon to implement it. Further, when attempting to save power, the Vcc,min characteristic measurement becomes much more critical for the read circuitry, as that is the portion of the circuitry that is active most often.
FIG. 3 depicts another known SRAM cell 20 arrangement that uses ten transistors (10T). In this form, the circuit has two read ports, one coupled to each storage node SN1 and SN2 of the 6T cell 10. Each read port 22 and 24 has a separate control line (RWL1 and RWL2) and a separate pull down NMOS transistor and pass gate NMOS transistor. The two read bit lines RBL1 and RBL2 are coupled by the pass gate transistors RPG1 and RPG2 to the pull down transistors RPD1 and RPD2 respectively. The pull down transistors each have a gate terminal coupled with a respective storage node SN1 and SN2. The read operations may be performed independently or simultaneously. The use of the two read ports provides additional flexibility and allows two outputs to be read from the cell simultaneously.
FIG. 4 depicts a bit cell layout for the single port, 6T bit cell 10. In FIG. 4, an N type well is formed in a semiconductor substrate, which may be, for example, a P-type substrate, or a P doped epitaxially formed silicon layer over an insulator (SOI). The dashed areas depict the polysilicon gates, contacts are shown and the active areas 31 are shown for the NMOS and PMOS transistors. The transistors are labeled at their gates; PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2 form the 6 T single port bit cell. The cell has a pitch labeled Y1-pitch in the Y direction and a pitch labeled X1-pitch in the X direction. The contacts are labeled with the appropriate signal, word line contacts are formed for both the PG-1 and PG-2 transistors, and the cell area is defined to include these contacts and the bit line and power contacts. Two storage nodes are formed in the bit cell. The layout corresponds to the SRAM bit cell 10 of FIG. 1.
Similarly, a layout for the two port 8T bit cell 12 is depicted in FIG. 5. In this cell layout, the read port is added to the single port. Active areas 31 are shown. The same 6 transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2 are shown now forming the write port and in addition, the layout includes the read port transistors RPG-1 and RPD-1. The read bit line and read word line contacts are shown at the right end of the cell. An N well is formed to form the channel for the two PMOS pull-up transistors, the remaining NMOS transistors are formed in a P-type substrate. The cell has a Y direction pitch labeled Y2 pitch, and an X direction pitch labeled X2-pitch.
The SRAM arrays are combined with other functions to form a “core”. A design core is a functional block that may be used in a standardized design approach by placing it on an integrated circuit along with other user defined functions to define a new integrated circuit. Because the design core is completely understood and verified for manufacture already, and is typically calibrated to one or more semiconductor processes provided by, for example, a semiconductor foundry, the use of these cores allows a new functional device to be rapidly and inexpensively implemented. Because many of the design cores include a processor, microprocessor, digital signal processor or other computing function, SRAM memory is often also included. The SRAM may be broken into a general purpose data store and a level one (L1) cache. Cache memory may store instructions or data that the processor has used or expects to use soon or that is to be reused. For example, this occurs while executing a loop operation. The use of cache memory reduces the time the processor must wait for words to be retrieved from an off chip memory location. The use of embedded SRAM cache memory on board the integrated circuit and placed near the processor or logic function allows very rapid retrieval of necessary data words or program instructions, thus providing additional processor performance.
FIG. 6 depicts in a block diagram the functional blocks of a single core integrated circuit 41 with embedded SRAM arrays. In FIG. 6, a first portion of the transistor devices (and there are thousands of transistors on a state of the art integrated circuit) is used to form input output or I/O devices 43. Because the I/O devices are coupled to external pins and signal traces and have to drive larger currents, these transistors are usually formed using larger area devices with higher gains and thicker gate dielectrics to carry additional current. A second portion of the integrated circuit 41 is logic 45. Since the logic transistors need to have high speed and low power consumption, these devices may be small, have thinner gate dielectrics than the I/O portion, and may have lower threshold voltages. Threshold voltages may be adjusted using implants including, for example, the lightly doped drain (LDD) ion implants and additional pocket implants to tailor the device characteristics, as is known in the art.
A first single port embedded SRAM array 47 is shown in FIG. 6. The conventional methods for processing such a device use the same gate dielectric material and the same implant processing for the SRAM bit cells as that used in the logic portion 45. A second embedded SRAM array 51, this one a two port 8T bit cell array (2P-8T), is shown. Again the conventional method for producing this single core integrated circuit is to use the same gate dielectric and the same LDD and pocket ion implant masks to complete all portions of the device.
FIG. 7 depicts an alternate approach to a single core integrated circuit 51 with embedded SRAM known in the art. In this block diagram, again there is a portion 43 that is for I/O devices. A second portion 45 is provided that has logic devices, with transistors formed using logic rules for a gate dielectric (first gate oxide thickness) and an NMOS LDD Mask for LDD ion implantation and pocket implant steps. In FIG. 7, an SRAM portion 53 is shown which is a first embedded SRAM array. This array 53 is a single port SRAM formed using a set of SRAM design rules, including the same gate dielectric as before, but now using a second NMOS LDD mask (NLDD-2) for the SRAM transistors for LDD and pocket ion implant steps.
Further, in FIG. 7, a portion 55 is provided with a second embedded SRAM array formed using the same gate dielectric thickness and having the second NMOS LDD-2 mask step for the 6T write transistors and for the 2T read port transistors. Using the different implant masks for the LDD and pocket implants allows the process to form transistors for the logic portion transistors and in the transistors for the SRAM portions with different performance characteristics on the same core.
Recently, the dual port 8T SRAM cell has become very popular for implementing level 1 (L1) cache in a core. The need to lower the power, and especially the standby power, of the SRAM arrays has also become an issue. As semiconductor processes advance and device sizes continue to shrink, the ability to reduce power consumption has reached critical limitations. The SRAM array needs to be stable and retain data, however the usual approach of continuously lowering the supply power to reduce power (Vcc,min) is not compatible with the goals of stability and reducing standby leakage current Isb.
The continuing and increasing demand for low power integrated circuits, particularly for more complicated battery powered, portable devices, requires that SRAM cells have good power consumption characteristics. One measure of the power consumption is the standby leakage current Isb. When the SRAM cell is not being used, the SRAM array may be placed in a standby mode. The leakage current consumed during standby, Isb, should be minimized. Further, it is known in the art to reduce power consumed in CMOS circuitry during standby mode by reducing the positive power supply as far as possible. The metric used to determine this potential is referred to as “Vcc, min.”. It is clearly advantageous to provide SRAM cells with a low Vcc,min value. This is difficult to do reliably for the 6T storage cells, however, due to process variations and other constraints increasingly imposed by shrinking device sizes.
Thus, there is a continuing need for a single or dual core integrated circuit either improved embedded SRAM bit cell structures that has a lower standby leakage current Isb; improved Vcc,min for lower standby power, and improved access speed particularly during read operations, while remaining compatible with state of the art semiconductor processes for fabricating integrated circuits, without adding significant steps or significant added costs.